Notice of Violation of IEEE Publication PrinciplesCost minimization for ASIC hybrid BIST designs

Abstract

In this paper are presented different methods for a hybrid BIST cost optimization for single-core designs. For selecting the optimal switching moment from the pseudorandom test mode to the stored test mode, two algorithms were proposed for calculating the complete cost curve of the different hybrid BIST solutions. The first one is a straightforward method based on using traditional fault simulation and test pattern generation. The second one is based on fault table manipulations and uses test compaction. The experimental simulated results demonstrate the feasibility of the approach and the efficiency of the fault table based cost calculation method.