Design and Implementation of CRC Based on FPGA

Abstract

In modern communication systems, high-speed and high-reliability is the two most important yardsticks. but digital code may be distorted during the transmission, so we should and must encoding some redundant bits to assure the received code correct to enhance the reliability of the communication systems. This thesis is to expound the encoding and decoding theory of CRC and design it by VHDL language and verify the correctness of CRC.