An efficient Viterbi decoder design for DMB receiver

Abstract

The efficient Viterbi decoder that supports full data-rate output of DMB system was proposed. In this paper, SST scheme was adopted for Viterbi decoder with puncturing to reduce the power consumption. Puncturing vector tables are modified and re-arranged to be designed by hardwired logic to save the system area. New re-scaling scheme is proposed and the proposed re-scaling scheme optimizes the wordlength of path metric memory and greatly reduces the computational load for re-scaling by controlling MSB of path metric memory. Another saving of computation is done by proposed algorithm for branch metric calculation, which makes use of pre-calculated metric values. The designed Viterbi decoder was synthesized using SAMSUNG 0.35u standard cell library and occupied small area and showed low power consumption.