Study for the electrical quality degradation of N-channel VDMOSFET transistor induced by electrical stress

Abstract

The aim of this work is to study the behavior of a VDMOSFETs N-channel transistor pre-exposed to electrical stress where experimental results show a consistent degradation in the devices characteristics. The resultant aging in the studied devices have been attributed to trapped holes, trapped electrons and interface states. The electrical stress was applied using the two well-known techniques, widely used in the literature: CVS (Constant Voltage Stress) and hot-carriers injection stress. Degradations coming from the electrical stress were followed by a measurement for the gate to source capacitance, the threshold voltage and the Flat Band voltage before and after each stress dose.