Sub-Terahertz 300GHz Amplifier on CMOS for Ultra-High Data-Rate Wireless Communications

Abstract

This work presents a 300GHz amplifier in 65-nm standard bulk CMOS. The amplifier has gain from 273 to 301GHz, and the peak gain is 21dB at 298GHz. The amplifier has 16-stage positive-feedback common-source topology. The power consumption is 35.4mW from a 1.2V supply. Transistor (1μm×8) layout is optimized for minimizing gate and channel resistance to increase gain corner frequency from 250GHz (conventional design kit-based transistor measurement result) to 270GHz, and $f$max from around 300GHz (design kit based) up to 317GHz. The DC-blocking capacitors are 10fF finger-based design which has lower loss than conventional MOM capacitors.