{"title":"Development of a RISC-based, high-performance, miniature computer system (for SDI interceptor)","authors":"T. Hanson, B. K. Smith, C. Shelor","doi":"10.1109/DASC.1990.111364","DOIUrl":null,"url":null,"abstract":"A high-throughput, reduced-instruction-set-computer (RISC)-based, lightweight computer system has been developed. The hardware and software design and fabrication efforts to produce that machine are described. The effects of a RISC microprocessor in an embedded, real-time, data processing application are discussed. It is shown that, in spite of the limitations of the selected CPU (minimal hardware interrupt capability, rigid memory architecture expectations, and complex interface timing requirements), a variety of hardware and software techniques were used to capitalize on the R3000's outstanding processing capability. The final result in an operating, high-performance computer, capable of real-time, embedded processing.<<ETX>>","PeriodicalId":141205,"journal":{"name":"9th IEEE/AIAA/NASA Conference on Digital Avionics Systems","volume":"12 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"1990-10-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"0","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"9th IEEE/AIAA/NASA Conference on Digital Avionics Systems","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/DASC.1990.111364","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 0
Abstract
A high-throughput, reduced-instruction-set-computer (RISC)-based, lightweight computer system has been developed. The hardware and software design and fabrication efforts to produce that machine are described. The effects of a RISC microprocessor in an embedded, real-time, data processing application are discussed. It is shown that, in spite of the limitations of the selected CPU (minimal hardware interrupt capability, rigid memory architecture expectations, and complex interface timing requirements), a variety of hardware and software techniques were used to capitalize on the R3000's outstanding processing capability. The final result in an operating, high-performance computer, capable of real-time, embedded processing.<>