A 500MHz-BW −52.5dB-THD Voltage-to-Time Converter utilizing a two-step transition inverter

Abstract

This paper presents a 500MHz-BW -52.5dB-THD Voltage-to-Time Converter (VTC) in 28nm CMOS. A two-step transition inverter raises the VT conversion gain to 100ps/V which is >10× higher than a conventional current-starved inverter. The number of required inverter stages is reduced to 4 from 64, resulting in 1/8 conversion latency and thus 13.2dB THD suppression at 500MHz full Nyquist. A test-chip measurement successfully demonstrates -52.5dB THD at 500MHz without sampling-and-hold. Effective VT conversion linearity is measured to be 1ps/LSB with INL/DNL of less than +/-0.53LSB. The proposed VTC consumes 84μm2 silicon area and 0.18mW at 1GS/s.