Bit-serial pipeline synthesis for multi-FPGA systems with C++ design capture

Abstract

Developing applications for a large-scale configurable system composed of state-of-the-art FPGA technology is a grand challenge. FPGAs are inherently resource limited devices in terms of logic, routing, and IO. Without a careful circuit implementation strategy, one would waste a large portion of the potential capacity of the configurable hardware. Also, high-level design entry support is essential for such large-scale hardware. A C++ design tool has been implemented which maps the computational algorithms onto bit-serial pipeline networks which exhibit high performance and maximize the device utilization of each FPGA. With this tool, the designer is able to develop applications in a very short time, and also is able to try out different algorithm implementations easily to see the trade-offs in terms of performance and hardware size instantaneously. Based on this C++ design tool, a number of DSP applications such as 1D and 2D filters, adaptive filters, Inverse Discrete Cosine Transform, and digital neural networks were designed.