Spatial-Temporal Transformation of Matrix and Multilayer Algorithms of Binary Number Multiplication

Abstract

The paper conducted analysis of matrix and multilayer structures of algorithms for multiplication of binary numbers and determined their advantages and disadvantages. The hardware and time characteristics of matrix and multilayer binary number multipliers with the use of improved structures of single-digit full and half adders are investigated. Using theory of spatio-temporal graphs recursive multistep structures of the multipliers are developed. The analytical expressions for evaluation of the complexity of developed multiplier structures are obtained. It is determined that the algorithmic and conveyor structures of the multipliers have high speed and require significant hardware complexity, in contrast to the proposed multi-cycle structures that have significantly lower performance, but the hardware complexity and the corresponding occupied area on the crystal are minimal. Synthesis of developed multiplier structures on the Xilinx FPGA is performed and the convergence of theoretical and practical results of researches is shown.