{"title":"High-Throughput LDPC Decoder for Long Code-Length","authors":"T. Ishikawa, K. Shimizu, T. Ikenaga, S. Goto","doi":"10.1109/VDAT.2006.258134","DOIUrl":null,"url":null,"abstract":"We have designed and implemented the LDPC decoder with memory-reduction method to achieve high-throughput and practical hardware size for long code-length. The decoder decodes (3,6)-11520-bit regular LDPC codes using modified min-sum algorithm. The decoder achieves a throughput of 312 Mb/s at an operating frequency of 69 MHz with 20 iterative decoding. The gate count is 2M gates","PeriodicalId":356198,"journal":{"name":"2006 International Symposium on VLSI Design, Automation and Test","volume":"87 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2006-04-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"3","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"2006 International Symposium on VLSI Design, Automation and Test","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/VDAT.2006.258134","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 3
Abstract
We have designed and implemented the LDPC decoder with memory-reduction method to achieve high-throughput and practical hardware size for long code-length. The decoder decodes (3,6)-11520-bit regular LDPC codes using modified min-sum algorithm. The decoder achieves a throughput of 312 Mb/s at an operating frequency of 69 MHz with 20 iterative decoding. The gate count is 2M gates