A 1Tb/s 3W Inductive-Coupling Transceiver Chip

Abstract

A 1Tb/s 3W inter-chip transceiver transmits clock and data by inductive coupling at a clock rate of 1GHz and data rate of 1Gb/s per channel. 1024 data transceivers are arranged with a pitch of 30 mum in a layout area of 1mm2. The total layout area including 16 clock transceivers is 2mm2 in 0.18 mum CMOS and the chip thickness is reduced to 10 mum. Simple yet accurate model of inductive coupling is utilized for transceiver design. Bi-phase modulation (BPM) is employed for the data link to improve noise immunity, reducing power in the transceiver. 4-phase time division multiplexing (TDM) reduces crosstalk and channel pitch. The BER is lower than 10-13 with 150ps timing margin.