A First Analysis of a Dynamic Memory Allocation Controller (DMAC) Core

Abstract

Networking performance continues to grow but processor clock frequencies have not. Likewise, the latency to primary memory is not expected to improve dramatically either. This is leading computer architects to reconsider the networking subsystem and the roles and responsibilities of hardware and the operating system. This paper presents the first component of a new networking subsystem where the hardware is responsible for buffering, when necessary, messages without interrupting or involving the operating system. The design is presented and its functionality is demonstrated. The core on an FPGA is exercised with a synthetic stream of messages and the results show that the analytical performance model and measured performance agree.