A high-speed analog min-sum iterative decoder

Proceedings. International Symposium on Information Theory, 2005. ISIT 2005. Pub Date : 2005-10-31 DOI:10.1109/ISIT.2005.1523649

S. Hemati, A. Banihashemi, C. Plett

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引用次数: 4

Abstract

Current-mode circuits are presented for implementing analog min-sum (MS) iterative decoders. Proposed circuits are devised based on current mirrors. Therefore, in any fabrication technology that accurate current mirrors can be designed, analog MS decoders can be implemented. The functionality of the proposed modules was verified by implementing an analog MS decoder for a (32,8,10) regular LDPC code in 0.18-mum CMOS technology. In low signal to noise ratios when the circuit imperfections are dominated by the noise of the channel, the measured error correcting performance of this chip in steady-state condition surpasses that of the conventional MS decoder, and is close to the performance predicted by the earlier work on the dynamics of the continuous-time analog decoding by Hemati and Banihashemi, ISIT2004. At a throughput of 24 Mb/s, loss in the coding gain compared to the conventional MS decoder at BER of 10-3 is about 0.3 dB. To the best of our knowledge, this decoder has the highest throughput and the lowest power/speed ratio among the reported analog CMOS iterative decoders

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高速模拟最小和迭代解码器

本文介绍了用于实现模拟最小和（MS）迭代解码器的电流模式电路。所提出的电路是基于电流镜设计的。因此，在任何可以设计出精确电流镜的制造技术中，都可以实现模拟 MS 解码器。通过在 0.18 微米 CMOS 技术中实现 (32,8,10) 规则 LDPC 代码的模拟 MS 解码器，验证了所提模块的功能。在信噪比较低的情况下，当电路缺陷由信道噪声主导时，该芯片在稳态条件下的测量纠错性能超过了传统 MS 解码器，并接近 Hemati 和 Banihashemi（ISIT2004）早期关于连续时间模拟解码动态的工作所预测的性能。在吞吐量为 24 Mb/s 时，与误码率为 10-3 的传统 MS 解码器相比，编码增益损失约为 0.3 dB。据我们所知，在已报道的模拟 CMOS 迭代解码器中，该解码器具有最高的吞吐量和最低的功率/速度比。

本文章由计算机程序翻译，如有差异，请以英文原文为准。

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Proceedings. International Symposium on Information Theory, 2005. ISIT 2005.

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