Behavioral emulation of synthesized RT-level descriptions using VLIW architectures

Abstract

Describes techniques that allow VLIW architectures to be used for the behavioral emulation of RT-level descriptions. The starting point of the techniques is a behavioral description at the algorithmic level, e.g. VHDL. This description is transformed into RT-level descriptions of the datapath and controller. The controller is given as a finite state machine. We show how to map these descriptions onto assembly code that can be executed on a VLIW microprocessor. We found the Texas Instruments TMS320C6x series of DSP chips to be suitable candidates for the mapping.