Reliability Evaluation of Polyphase-filter based Decimators Implemented on SRAM-FPGAs

Abstract

Decimation is widely used in digital communication systems to reduce the oversampling rate of the base band signal. The structure of Poly Phase Filters (PPFs) provides an efficient implementation of the decimator. This paper studies the effects of Single Event Upsets (SEUs) on PPFs based decimators implemented on SRAM-FPGAs. Fault injection experiments are performed to evaluate the reliability of the decimator to SEUs on filter coefficients and on the configuration memory. For the first part, experiment results show that only SEUs on the two most significant bits would cause non negligible SNR loss in the output. For SEUs on the essential bits in the configuration memory, about 20% of them would affect the results, among which 70% of the SEUs would cause negligible SNR loss. The percentage of SEUs that cause a SNR loss larger than 5dB are 7%, 13% and 16% for decimation rates of 16, 8 and 4, respectively. This can be explained as the decimator is composed of a number of parallel filters that is equal to the decimation rate, and each filter contributes a fraction of the final output. Therefore, a SEU on one filter would not cause large degradation to the decimated signal, and the larger the decimation rate is, the smaller the degradation of decimated signal introduced by the SEU.