A Method for IC Layout Verification

Abstract

A method for MOS integrated circuit layout verification based on net list extraction and logic simulation is presented. The net list elements are on the gate level or higher, defined by the user. A self developed net list extractor, NETEX, is described. NETEX is interfaced to a commercially available layout system and logic simulator. Results show that this is a fast and reliable way of connectivity checking. Limitations and further improvements are discussed.