Stress Induced Voiding Behavior of Electroplated Copper Thin Films in Highly Scaled Cu/low-k interconnects

Abstract

Stress Induced Voiding (SIV) is strongly influenced by electroplating copper process (ECP) hardware setting: edge bevel removal (EBR, post plating cell of ECP hardware). The study indicated that more EBR will induce poor SIV performance. This phenomenon could be explained by the radius of curvature of a 300 mm patterned wafer. More outliers was observed at the higher level via. This suggested that the thermally induced stress in the via was increased with higher metallization layers. Regarding to the impact of metal width, only the widest metal width plus more EBR has highest RC drift, suggested that wider metal provides a sufficient vacancy source to form voids by more compressive stress gradient distribution beneath the via then cause higher RC drift.