Implementation and Functional Verification of RISC-V Core for Secure IoT Applications

Abstract

In the world of technology we live in, there is a huge increase in the number of internet of things (IoT) devices leading to a tremendous amount of data being sent. This wireless data is prone to eavesdropping and being hacked. The contribution of this work is the design of a System on Chip (SoC) with a processor based on the instruction set architecture (ISA) of reduced instruction-set computer (RISC-V). The system focuses on the security of data between IoT end-nodes. For SoC verification, a Universal Verification Methodology (UVM) environment is used for covering most of the functionality and security aspects to guarantee a sufficient level of trust in the implemented SoC.