M. Alderighi, F. Casini, S. D'Angelo, M. Mancini, D. Merodio Codinachs, S. Pastore, G. Sorrenti, L. Sterpone, R. Weigand, M. Violante
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引用次数: 6
Abstract
We describe a methodology for analyzing the robustness of circuits implemented by SRAM-based FPGAs against the accumulation of soft errors within the configuration memory. A detailed analysis of the fault injection data is presented.