Performance evaluation of hardware models of Advanced Encryption Standard (AES) algorithm

Abstract

In today's world most of the communication is done using electronic media. Data Security plays a vital role in such communication. Hence, there is a need to protect data from malicious attacks. Advanced Encryption Standard (AES), also known as Rijndael, is an encryption standard used for securing information. AES is a block cipher algorithm that has been analyzed extensively and is now used widely. The hardware implementation of AES algorithm is faster and more secure than software implementation. There are different hardware models to implement the Rijndael Encryption core. This paper addresses the performance of Rijndael AES Encryption algorithm of key length 128 bits. Two hardware models based on HDL and IP core are used to evaluate the performance of the algorithm. The encryption time and also the performance metrics such as size, speed and memory utilization are evaluated, using these models. Results are compared to a reference model and have shown an increase in the throughput per slice measure.