90 nm generation, 300 mm wafer low k ILD/Cu interconnect technology

Proceedings of the IEEE 2003 International Interconnect Technology Conference (Cat. No.03TH8695) Pub Date : 2003-06-02 DOI:10.1109/IITC.2003.1219699

C. Jan, J. Bielefeld, M. Buehler, V. Chikamane, K. Fischer, T. Hepburn, A. Jain, J. Jeong, T. Kielty, S. Kook, T. Marieb, B. Miner, P. Nguyen, A. Schmitz, M. Nashner, T. Scherban, B. Schroeder, P. Wang, R. Wu, J. Xu, K. Zawadzki, S. Thompson, M. Bohr

引用次数: 18

Abstract

This paper presents a 90 nm generation and 300 mm wafer size interconnect technology with 7 layers of Cu metallization and low k ILD. Carbon doped oxide (CDO) low k ILD is used to achieve > 20% inter- and intra-layer capacitance improvement and 25-30% RC improvement over 130 nm generation SiOF interconnect process with equivalent electromigration performance.

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90纳米代，300毫米晶圆低k ILD/Cu互连技术

本文提出了一种采用7层铜金属化和低k ILD的90nm代300mm晶圆尺寸互连技术。在具有等效电迁移性能的130 nm SiOF互连过程中，采用碳掺杂氧化物(CDO)低k ILD可实现> 20%的层间和层内电容改善和25-30%的RC改善。

本文章由计算机程序翻译，如有差异，请以英文原文为准。

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来源期刊

Proceedings of the IEEE 2003 International Interconnect Technology Conference (Cat. No.03TH8695)

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