A High Precision Time-to-Digital Converter based on Multi-chain Interpolation with a Low Cost Artix-7 FPGA

Abstract

This paper presents a high precision Time-to-Digital Converter (TDC) implemented in a low-end, low power Field Programmable Gate Array (FPGA). It applies the interpolation method for fine time measurement, and a multi-chain tapped-delay line (TDL) structure is used to achieve high precision. To avoid bubble error and to decrease dead time, a Wallace-tree encoder with pipeline structure is utilized in each chain, for encoding the 234-bit thermometer code from the delay taps. A double-channel TDC with different numbers of chains is implemented in a Xilinx Artix-7 100T FPGA to verify the design concept and to study the performances in detail. Test results show that with eight chains implemented for each channel, the best precision of leading-edge measurement (channel to channel) can reach 6.4 ps in root mean square (RMS). The LUT resource occupancy of the double-channel TDC (together with auxiliary circuits) is about 9.77%, which shows good potential for expanding the channel numbers for high density, low cost applications.