A parameter to measure the efficiency of FPGA based logic synthesis tools

Abstract

In FPGA-based designs, the number of logic cells (LCs) needed is an important criterion to judge whether a design is good or not. The total number of LCs required to implement a circuit differs vastly from tool to tool. Normally, vendor software use more LCs than the theoretical maximum needed by functional decomposition to implement a circuit. Academic software use less LCs. So far, we are not aware of any technique that would give a quantitative measure to judge the comparable silicon area efficiency of a logic synthesis tool. This paper presents a technique to calculate the minmax number of logic cells (Q) needed to implement a logic circuit. It is proved that the total number of LCs needed to implement a circuit is less than or equal to Q.