A rail-to-rail, constant gain CMOS op-amp

Abstract

A rail-to-rail constant gain CMOS operational amplifier was designed by using complementary differential input stage and current compensation skills. The chip was implemented by a 0.35/spl mu/m 1P4M CMOS standard logic process. The measurement results show that the chip can achieve 110dB gain, 13.6MHz bandwidth, and 1.275mW power consumption, when operating at 3V and 35pF load.