A 0.13-/spl mu/m CMOS Ultra-Low Power Front-End Receiver for Wireless Sensor Networks

Abstract

This paper presents an ultra-low power monolithic CMOS RF receiver, consisting of current re-use common gate LNA with inductive feedback gm-boosting, and followed by balanced I/Q mixers. The receiver is fabricated in a 0.13-mum CMOS digital process operating at 2.45 GHZ. The measurement results show that the RF receiver achieves a gain of 20 dB and a noise figure of 7.5 dB at 2 MHz. Input 1-dB compression point is -19 dBm and IIP3 is -10 tlBm, with 0.4 mA total current consumption from a 1.5-V supply.