A Design of FPGA Acceleration System for Myers bit-vector based on OpenCL

Abstract

A FPGA-based acceleration system has been designed based on OpenCL framework. The acceleration of Myers bit-vector algorithm in system is achieved by a dynamic programming way, and it has been applied to the high-throughput sequencing technology. The heterogeneous computing between X86 platform and FPGA platform, similar to heterogeneous computing between between X86 platform and FPGA platform, eliminates the bandwidth limitations of data transmission between two platforms with the third-generation PCI Express X8. As the internal data transmission bus in the FPGA, the Advanced Extensible Interface(AXI) bus can make full use of the bandwidth of dynamic random access memory(DRAM), because its clock frequency can reach 240Mhz after optimization and the data-width increases to 512bit. Furthermore, the acceleration system completes a global alignment in one clock cycle in pipeline working mode. These advantages allow this design to achieve 70 million global alignments of short gene sequence per second with only one MBV module.