On an approach in implementing DSP algorithms for digital hearing aids; a noise reduction core case study

Abstract

One of the major problems for hearing aid users is surrounding noise. The objective of the project is to design a noise reduction hardware (integrated circuit) for digital hearing aids. Instead of relying on separate algorithm and hardware (integrated circuit) developments, a design flow that integrates the developments of DSP algorithms and FPGA hardware to increase performance and reduce development time is illustrated. A noise reduction core using integrated adaptive beamformer and feedback control is designed and tested as an example.