Realization of FPGA-based two dimensional discrete cosine transform

Proceedings of the Sixteenth National Radio Science Conference. NRSC'99 (IEEE Cat. No.99EX249) Pub Date : 1999-02-23 DOI:10.1109/NRSC.1999.760887

H.B. Helal, A. Salama, S. Mashali

引用次数: 1

Abstract

A new algorithm for the computation of a 2-D DCT is presented, the computational complexity as measured in terms of the number of multiplications and additions is kept to a minimum, the algorithm is amenable to implementation using field programmable gate arrays (FPGAs). An example of a 4/spl times/4 2-D DCT is presented, and its performance is evaluated.

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基于fpga的二维离散余弦变换实现

提出了一种计算二维DCT的新算法，该算法以乘法和加法的数量为衡量标准，计算复杂度保持在最小，该算法适用于使用现场可编程门阵列(fpga)实现。给出了一个4/ sp1 × /4二维DCT的实例，并对其性能进行了评价。

本文章由计算机程序翻译，如有差异，请以英文原文为准。

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来源期刊

Proceedings of the Sixteenth National Radio Science Conference. NRSC'99 (IEEE Cat. No.99EX249)

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