Efficient signal integrity verification method of multi-coupled RLC interconnect lines with asynchronous circuit switching

Abstract

A new signal integrity verification method of integrated circuit interconnects with asynchronous circuit switching is presented. A ramp input is modeled with delayed step inputs. Then signal transient variations due to asynchronous input signal switching are accurately as well as efficiently determined by using traveling-wave-based waveform approximation (TWA) technique. It is shown that using 90nm technology, the signal timing and crosstalk of multi-coupled lines with asynchronous switching inputs have an excellent agreement with SPICE simulation but its computation time is several thousand times faster than that of SPICE simulation using generic segment-based RLC circuit model