Large scale input and output buffered ATM switch

Abstract

ATM switches, which serve as nodes in ATM public backbone networks, are required to have a large capacity due to the increase of traffic. This paper proposes a large-scale ATM switch architecture providing 160 Gbit/s switching capability. It is such that the output buffered switch elements are expanded in square grids. Our switch architecture achieves non-blocking and multi-QoS guarantee. As a way to ensure multi-QoS, we employ a stop-shape-go (SSG) congestion control method and its performance is evaluated by simulation.