A 225mW 28Gb/s SerDes in 40nm CMOS with 13dB of analog equalization for 100GBASE-LR4 and optical transport lane 4.4 applications

M. Harwood, S. Nielsen, A. Szczepanek, Richard Allred, Sean Batty, M. Case, S. Forey, K. Gopalakrishnan, Larry Kan, B. Killips, Parmanand Mishra, Rohit Pande, H. Rategh, A. Ren, Jeff Sanders, A. Schoy, Richard Ward, Martin Wetterhorn, N. Yeung
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引用次数: 31

Abstract

A key challenge in optical networking is the development of low-power transceivers that interface to optical sub-assemblies (TOSAs & ROSAs). While SiGe technologies are often selected for jitter performance with optical links, especially on the egress path to the transmit optics, lower-power and higher levels of digital integration often result from CMOS approaches . This paper describes a generic CMOS 25-to-30Gb/s SerDes for use within CDR or gearbox applications, targeting the draft requirements of the OIF 28G-VSR standard and suitable for both 100GBASE-LR4/OTL4.4 gearbox and retiming applications, including CFP and CFP2.
225mW 28Gb/s SerDes, 40nm CMOS, 13dB模拟均衡,适用于100GBASE-LR4和光传输通道4.4应用
光网络的一个关键挑战是开发与光子组件(tosa和rosa)接口的低功耗收发器。虽然SiGe技术通常用于光学链路的抖动性能,特别是在传输光学的出口路径上,但低功耗和高水平的数字集成通常来自CMOS方法。本文描述了用于CDR或变速箱应用的通用CMOS 25- 30gb /s SerDes,针对OIF 28G-VSR标准的草案要求,适用于100GBASE-LR4/OTL4.4变速箱和重定时应用,包括CFP和CFP2。
本文章由计算机程序翻译,如有差异,请以英文原文为准。
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