Driver Chip Design Considerations for VRM Applications

2006 12th International Power Electronics and Motion Control Conference Pub Date : 2006-08-01 DOI:10.1109/EPEPEMC.2006.4778574

Shih-hui Chen, Chung-Lung Pai, Dan Y. Chen, Jing-meng Liu, C. Juang

引用次数: 0

Abstract

In this paper, a power loss model of VRMs will first be given. Actual power loss distribution on VRMs will be estimated for various VRM conditions. Comments will be made from the observations of the results and suggestions be made from the point of view of gate driver chip design. Discussion of future improvement possibilities is presented.

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VRM应用的驱动芯片设计注意事项

本文首先给出了vrm的功率损耗模型。根据各VRM节点的实际情况，估算各VRM节点的实际损耗分布。从结果的观察和从栅极驱动芯片设计的角度提出建议。讨论了未来改进的可能性。

本文章由计算机程序翻译，如有差异，请以英文原文为准。

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来源期刊

2006 12th International Power Electronics and Motion Control Conference

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