PPBAM:A Preprocessing-based Power-Efficient Approximate Multiplier Design for CNN

Yifan Hu, Tao Huang, Run Run, Li Yin, Guolin Li, Xiang Xie
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Abstract

In the fields of CNN, there exists many multiply applications with one fixed operand. In view of such characteristics, this paper proposes a preprocessing-based power-efficient approximate multiplier (PPBAM) design for CNN. In the proposed design, the fixed operand is preprocessed to avoid additional dynamic power consumption due to repeated processing. To reduce the number of the partial products, the first ‘1’ of both two operands are found and then the operands are truncated by a method named weak rounding. What's more, a sub multiplier array utilizing an approximate 4:2 compressor are proposed to calculate the truncation results with low power. The experimental results show that, with the same accuracy, on average, our design has a 30% improvement in power consumption compared with state-of-the-art approximate multiplier designs without additional latency and area.
PPBAM:一种基于预处理的CNN节能近似乘法器设计
在CNN领域中,存在着许多使用一个固定操作数的多重应用。针对这一特点,本文提出了一种基于预处理的CNN节能近似乘法器(PPBAM)设计。在所提出的设计中,对固定操作数进行预处理,以避免由于重复处理而产生额外的动态功耗。为了减少部分积的数量,首先找到两个操作数的第一个“1”,然后通过一种名为弱舍入的方法截断操作数。此外,还提出了一种利用近似4:2压缩器的子乘法器阵列来计算低功耗的截断结果。实验结果表明,在相同的精度下,平均而言,我们的设计与最先进的近似乘法器设计相比,功耗提高了30%,而没有额外的延迟和面积。
本文章由计算机程序翻译,如有差异,请以英文原文为准。
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