A comparative study of high performance dynamic comparators using strained silicon technology

Abstract

Dynamic comparators are widely being used in high speed Analog to Digital Converters (ADC) such as flash ADC's because of its low voltage, low power, high speed and area efficiency. In this paper, an analysis on the delay and power performance of strained silicon CMOS technology based dynamic comparators will be presented. To compare the performance of dynamic comparators, test circuits were simulated using 45nm high performance and low power technologies with a supply voltage of 0.8V using spice tools. Using circuit simulations, the overall improved characteristics of double tail dynamic comparator are demonstrated in comparison to those of the traditional as well as several state of the art dynamic comparators. The simulation results shows that in the dynamic double tail comparator both the power consumption and the time delay are reduced significantly.