High Performance and Hardware Efficient Stochastic Computing Elements for Deep Neural Network

Abstract

Three high performance and hardware efficient stochastic computing elements are proposed for the implementation of deep neural network. A hybrid stochastic multiplier which combines unipolar coding and bipolar coding is proposed to achieve efficient trade-off between high accuracy and low hardware consumption. Then, a stochastic accumulative parallel counter is present to achieve high accuracy stochastic-to-binary conversion with much less hardware consumption. Finally, a stochastic ReLU function is designed to precisely realize ReLU function in stochastic computing without approximate error.