A fast, fully verifiable, and hardware predictable ASIC design methodology

Abstract

In this paper, a fast, fully verifiable, and hardware predictable ASIC design methodology is proposed and demonstrated for the Vertical Slit FET (VeSFET) based integrated circuits. The key enablers of this methodology are the unique and powerful capabilities of pillar-based two-side accessible transistor arrays and monolithic 3D integration. VeSFET is a successfully fabricated transistor of this kind. In the proposed methodology, the circuit is first designed on a 3D FPGA platform using a conventional FPGA design flow. With a little extra Back End of Line (BEOL) masking cost, the design implemented on the 3D FPGA is migrated to the final 2D ASIC, which has exactly the same performance and the verification tasks performed on the 3D FPGA platform remain valid for the final 2D ASIC. The 2D ASIC has the same layout as the silicon-proven 3D FPGA, which greatly mitigates the unpredictable factors of fabrication. The proposed methodology retains all the benefits of FPGA design flow. Eleven MCNC benchmark circuits were implemented. Comparing to the 2D FPGA, the performance of the final 2D ASIC implementation as well as the performance of the 3D FPGA design platform are on average 15% faster, consume 17% less power and 44% less area.