A new NoC architecture based on partial interconnection of mesh networks

Abstract

A new network on chip (NoC) topology called partially interconnected mesh network is proposed and a routing algorithm supporting the proposed architecture is also developed. The proposed architecture is based on standard mesh networks, here four extra bidirectional channels are added which remove the congestion and hotspots compare to standard mesh networks with fewer channels. The proposed architecture and routing algorithm are compared to measure performance benefits over standard mesh network in terms of delay and throughput. Significant improvement in delay (60% reduction) and throughput (60% increased) were observed when using the proposed network. An increase in number of channels makes the switches expensive and could increase the area and power consumption. However, the proposed network can be useful in high speed applications with some compromise in area and power.