A 40-GHz frequency divider in 0.18-/spl mu/m CMOS technology

2003 Symposium on VLSI Circuits. Digest of Technical Papers (IEEE Cat. No.03CH37408) Pub Date : 2004-03-30 DOI:10.1109/JSSC.2004.825119

Jri Lee, Behzad Razavi

引用次数: 239

Abstract

A frequency divider employs resonance techniques by means of on-chip spiral inductors to operate at high speeds. Configured as two cascaded /spl divide/2 stages, the circuit achieves a frequency range of 2.3 GHz at 40 GHz while consuming 31 mW from a 2.5-V supply.

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采用0.18-/spl mu/m CMOS技术的40 ghz分频器

分频器采用共振技术，通过片上螺旋电感器在高速下工作。配置为两个级联/spl分/2级，电路在40 GHz时达到2.3 GHz的频率范围，同时从2.5 v电源消耗31 mW。

本文章由计算机程序翻译，如有差异，请以英文原文为准。

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来源期刊

2003 Symposium on VLSI Circuits. Digest of Technical Papers (IEEE Cat. No.03CH37408)

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