FPGA Based Edge Detection: Integer Division Algorithm with a Constant Divisor

Abstract

The paper presents an integer division algorithm with a constant divisor. Its application is focused on the computation of Gaussian weighted average function in FPGA based edge detection. Investigated are the algorithm's highest clock frequency and the smallest count of clock cycles required to provide the integer division result. Proved is the algorithm's capability to guarantee mathematical exactness for the entire range of values computed in Gaussian filtering. Ten FPGA families of Intel (Altera) are used to obtain the experimental data.