A Novel Hardened Design of a CMOS Memory Cell at 32nm

Abstract

This paper proposes a new design for hardening a CMOS memory cell at the nano feature size of 32nm. By separating the circuitry for the write and read operations, the static stability of the proposed cell configuration increases more than 4.4 times at typical process corner, respectively compared to previous designs. Simulation shows that by appropriately sizing the pull-down transistors, the proposed cell results in a 40% higher critical charge and 13% less delay than the conventional design. Simulation results are provided using the predictive technology file for 32nm feature size in CMOS to show that the proposed hardened memory cell is best suited when designing memories for both high performance and soft error tolerance.