Development and Comparative Analysis of Delay Fault Models for Variants of High Speed CNT Interconnects at Submicron Technology

Abstract

Copper (Cu) has been meticulously used as an onchip connectivity material in VLSI chip design. This paper explores and investigates characteristics of carbon nanotubes (CNT) as high-speed VLSI interconnects. Delay faults are comparatively reduced in CNT interconnects with respect to Cu interconnects. It has been observed that variants of CNT interconnects experiences delay fault at quite later stage compared to Cu interconnects. SPICE based delay fault model has been considered here for fault analysis in on-chip interconnects. It has been depicted that SWCNT interconnect outperform compare to other CNT interconnects in terms of delay fault model analysis. The length of interconnect is varied from 1 μm to 100 μm for delay fault analysis at 16 nm technology node.