Design of complex systems with a VHDL based methodology

Abstract

The design of complex systems requires a solid methodology in order to avoid dangerous anarchy during the design phase and to increase the overall quality of the final product. The presented methodology is founded on the use of VHSIC hardware description language (VHDL) as a common modeling language. The authors discuss modeling techniques in different areas: memory devices, ASICs, mu -processors and buses. An overview of some internally developed tools is presented.<>