A low power fast wakeup flash memory system for embedded SOCs

Abstract

This paper describes a system level approach to achieve a flash memory system that would consume very little current (less than a 1µA) in standby mode and would wake up fast (∼1µs) for a random-access read operation. The paper mainly focuses how analog circuits and other flash memory components can be partitioned to achieve these specifications. In addition, design considerations for various circuits have also been illustrated.