Selected aspects of component modeling

Proceedings EURO-DAC '92: European Design Automation Conference Pub Date : 1992-11-01 DOI:10.1109/EURDAC.1992.246192

A. Pawlack

引用次数: 1

Abstract

Summary form only given. VHSIC hardware description language (VHDL) models should be defined along precise guidelines in order to guarantee their compatibility and efficiency. The author reports on the generation of component models and the quantitative analysis of models.<>

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组件建模的选定方面

只提供摘要形式。为了保证VHSIC硬件描述语言(VHDL)模型的兼容性和效率，必须按照精确的准则定义VHSIC硬件描述语言模型。作者报告了构件模型的生成和模型的定量分析。

本文章由计算机程序翻译，如有差异，请以英文原文为准。

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来源期刊

Proceedings EURO-DAC '92: European Design Automation Conference

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