Design Automation of Network-on-Chip Prototype on FPGA

Abstract

This paper addresses the automation process used in the synthesis of an optimized Network-on-Chip (NoC) design. The topology of a NoC and the number of nodes in the network may vary depending on the user requirement. The aim of automation is to faster the design process, perform resource utilization analysis, and prototype NoC architecture on to FPGA for any topology with the network size specified by user. This has been achieved through the open source language Python 3.0, and TCL console provided by Xilinx Vivado tool (2014.4). The results obtained are useful for testing NoC and prototyping it on to FPGA boards.