ASIC-FPGA Gap for a RISC-V Core Implementation for DNN Applications

Abstract

Recently, an emerging instruction set called RISC-V has been considered a paradigm in the computer architecture domain, which has easily got the attention of the hardware community. This is because it is fully open-source, which opens wide horizons for development and innovation. As deep learning applications (DL) are becoming more common, it is very important to evaluate the processors' performance handling such tasks. In these lights, a RISC-V core performance executing a DL task is evaluated. Also, the gap between its ASIC and FPGA implementations is measured in terms of power and area. The main finding is that ASIC achieves better optimization in both aspects more than the FPGA.