An area-efficient low-power SC integrator for very high resolution ADCS

Abstract

In this paper, a very area-efficient low-noise low-power correlated double sampled integrator has been presented. A fully differential class AB op-amp with preamplifier is designed with gain of 85dB, bandwidth of 12 Mrad/s and overall input referred noise floor of -171 dB. For attenuating the integrator's op-amp thermal noise, the input transconductance is kept as large as needed and also the bandwidth of the op-amp is decreased as much as possible without the need for large compensation capacitors as in the ordinary topologies are used. The integrator is used in the front-end of a 24 bit, fourth-order single-loop Delta-Sigma modulator for a bandwidth of 1000 Rad/s. The integrator power consumption is only 2.8 mW with a single 3.0V supply in 0.6-μm CMOS technology.