TSpice-Alecsis co-simulation

2002 23rd International Conference on Microelectronics. Proceedings (Cat. No.02TH8595) Pub Date : 2002-08-07 DOI:10.1109/MIEL.2002.1003335

Dejan Stefanovic, M. Sokolovic, P. Petkovic, V. Litovski

引用次数: 0

Abstract

Tanner Tools system (TTS) is a very useful tool for design automation. However, during the layout verification phase, the overall circuit is flattened and only transistor level simulation by TSpice simulator is possible. Obviously, this is not convenient especially regarding large digital or mixed circuits. Therefore, this paper describes a methodology for joint simulation based on Alecsis mixed-mode circuit simulator. The method is described on example of 64-level Calibrated Current-steering DAC.

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TSpice-Alecsis co-simulation

TTS是一个非常有用的设计自动化工具。然而，在布局验证阶段，整个电路是平坦的，只能通过TSpice模拟器进行晶体管级仿真。显然，这是不方便的，特别是对于大型数字或混合电路。因此，本文提出了一种基于Alecsis混合模电路模拟器的联合仿真方法。以64电平校准电流转向DAC为例介绍了该方法。

本文章由计算机程序翻译，如有差异，请以英文原文为准。

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来源期刊

2002 23rd International Conference on Microelectronics. Proceedings (Cat. No.02TH8595)

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