Low-power less-area bypassing-based multiplier design

Abstract

Low power less area bypassing based multipliers proposed on the bases of modified XOR gate in low cost low power bypassing based multiplier. On the bases of different tested samples our proposed design has average 49.41% less area, 13.6% reduced power dissipation, 2.36% less delay and 20.89% less power delay product in comparison to different types of multiplier for 4×4 and 8×8 bit.