Torus with slotted rings architecture for a cache-coherent multiprocessor

Abstract

The slotted ring is a point-to-point unidirectional connection for multiprocessor systems which resolves most of the problems associated with the bus system. However, the cycle time of the ring becomes the bottleneck when the system grows. Torus with slotted rings which is composed of multiple rings is proposed to reduce the cycle time of the resulting system. It is similar to the Wisconsin Multicube built by a grid of buses. The proposed architecture adopts a ring-map directory cache coherence scheme to avoid occupying too many rings during invalidation. Through performance evaluation, it is verified that the torus with slotted rings with ring-map directory scheme is better than the Wisconsin Multicube with the pure snooping scheme.